A transistor including a metal gate electrode and a high dielectric constant film (high-k film) has been known as a transistor to be formed in a logic unit of a next-generation microcomputer capable of miniaturization. As a method of forming such a transistor, a so-called gate last process has been known in which a dummy gate electrode is first formed on a substrate and the dummy gate electrode is then replaced by a metal gate electrode.
Moreover, as an electrically rewritable and erasable nonvolatile semiconductor storage device, a memory cell having a conductive floating gate electrode or a trapping insulating film surrounded by an oxide film under a gate electrode of a MISFET has been widely used. As a nonvolatile semiconductor storage device using a trapping insulating film, a MONOS (Metal Oxide Nitride Oxide Semiconductor) split gate cell has been known.
In the gate last process, elements are covered with an interlayer insulating film after forming a silicide layer on source/drain regions of each kind of MISFET, and an upper surface of the interlayer insulating film is then polished so that an upper surface of a gate electrode is exposed. For this reason, in the case in which a silicide layer is formed on a gate electrode constituting a memory cell and made of a semiconductor film, the process of forming the silicide layer needs to be carried out again after the polishing process.
In this case, when the silicide layer is formed on the upper surface of the gate electrode constituting the memory cell after the polishing process, a metal film is first deposited on the upper surface of the gate electrode by, for example, a sputtering method, and silicon forming the gate electrode is then reacted with the metal film to form the silicide layer.
In the technique described in the Patent Document 1 (Japanese Patent Application Laid-Open Publication No. 2014-154790), in the case of mounting a memory cell and a MISFET of a logic unit in a mixed manner, a silicide layer on the source/drain regions of the MISFET is first formed, a metal gate electrode of the MISFET is formed by the gate last process, and a silicide layer is then formed on the gate electrode of the memory cell.